Erick
146 lines
4.4 KiB
Systemverilog
146 lines
4.4 KiB
Systemverilog
import ram16::*;
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package ram512 (
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input [511:0]in;
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input [8:0]addr;
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input load;
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input clk
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output [511:0]out;
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);
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wire [15:0] [511:0] in0 = in;
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wire [31:15] [511:0] in1 = in;
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wire [47:31] [511:0] in2 = in;
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wire [63:47] [511:0] in3 = in;
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wire [79:63] [511:0] in4 = in;
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wire [95:79] [511:0] in5 = in;
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wire [111:95] [511:0] in6 = in;
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wire [127:111] [511:0] in7 = in;
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wire [143:127] [511:0] in8 = in;
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wire [159:143] [511:0] in9 = in;
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wire [179:159] [511:0] in10 = in;
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wire [191:179] [511:0] in11 = in;
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wire [207:191] [511:0] in12 = in;
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wire [223:207] [511:0] in13 = in;
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wire [239:223] [511:0] in14 = in;
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wire [255:239] [511:0] in15 = in;
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wire [271:255] [511:0] in16 = in;
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wire [287:271] [511:0] in17 = in;
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wire [303:287] [511:0] in18 = in;
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wire [319:303] [511:0] in19 = in;
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wire [335:319] [511:0] in20 = in;
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wire [351:335] [511:0] in21 = in;
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wire [367:351] [511:0] in22 = in;
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wire [383:367] [511:0] in23 = in;
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wire [399:383] [511:0] in24 = in;
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wire [415:399] [511:0] in25 = in;
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wire [431:415] [511:0] in26 = in;
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wire [447:431] [511:0] in27 = in;
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wire [463:447] [511:0] in28 = in;
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wire [479:463] [511:0] in29 = in;
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wire [495:479] [511:0] in30 = in;
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wire [511:495] [511:0] in31 = in;
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wire [8:0] [5:0] addr0 = in;
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wire [0:8] [5:0] addr1 = in;
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wire [15:0]out0;
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wire [15:0]out1;
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wire [15:0]out2;
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wire [15:0]out3;
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wire [15:0]out4;
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wire [15:0]out5;
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wire [15:0]out6;
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wire [15:0]out7;
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wire [15:0]out8;
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wire [15:0]out9;
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wire [15:0]out10;
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wire [15:0]out11;
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wire [15:0]out12;
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wire [15:0]out13;
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wire [15:0]out14;
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wire [15:0]out15;
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wire [15:0]out16;
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wire [15:0]out17;
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wire [15:0]out18;
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wire [15:0]out19;
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wire [15:0]out20;
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wire [15:0]out21;
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wire [15:0]out22;
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wire [15:0]out23;
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wire [15:0]out24;
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wire [15:0]out25;
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wire [15:0]out26;
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wire [15:0]out27;
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wire [15:0]out28;
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wire [15:0]out29;
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wire [15:0]out30;
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wire [15:0]out31;
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ram16 clstr0(in0, addr0, load, clk, out0);
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ram16 clstr1(in1, addr0, load, clk, out1);
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ram16 clstr2(in2, addr0, load, clk, out2);
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ram16 clstr3(in3, addr0, load, clk, out3);
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ram16 clstr4(in4, addr0, load, clk, out4);
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ram16 clstr5(in5, addr0, load, clk, out5);
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ram16 clstr6(in6, addr0, load, clk, out6);
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ram16 clstr7(in7, addr0, load, clk, out7);
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ram16 clstr8(in8, addr0, load, clk, out8);
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ram16 clstr9(in9, addr0, load, clk, out9);
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ram16 clstr10(in10, addr0, load, clk, out10);
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ram16 clstr11(in11, addr0, load, clk, out11);
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ram16 clstr12(in12, addr0, load, clk, out12);
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ram16 clstr13(in13, addr0, load, clk, out13);
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ram16 clstr14(in14, addr0, load, clk, out14);
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ram16 clstr15(in15, addr0, load, clk, out15);
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ram16 clstr16(in16, addr1, load, clk, out16);
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ram16 clstr17(in17, addr1, load, clk, out17);
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ram16 clstr18(in18, addr1, load, clk, out18);
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ram16 clstr19(in19, addr1, load, clk, out19);
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ram16 clstr20(in20, addr1, load, clk, out20);
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ram16 clstr21(in21, addr1, load, clk, out21);
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ram16 clstr22(in22, addr1, load, clk, out22);
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ram16 clstr23(in23, addr1, load, clk, out23);
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ram16 clstr24(in24, addr1, load, clk, out24);
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ram16 clstr25(in25, addr1, load, clk, out25);
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ram16 clstr26(in26, addr1, load, clk, out26);
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ram16 clstr27(in27, addr1, load, clk, out27);
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ram16 clstr28(in28, addr1, load, clk, out28);
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ram16 clstr29(in29, addr1, load, clk, out29);
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ram16 clstr30(in30, addr1, load, clk, out30);
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ram16 clstr31(in31, addr1, load, clk, out31);
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wire [15:0] [15:0] out0 = out;
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wire [15:0] [31:15] out1 = out;
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wire [15:0] [47:31] out2 = out;
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wire [15:0] [63:47] out3 = out;
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wire [15:0] [79:63] out4 = out;
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wire [15:0] [95:79] out5 = out;
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wire [15:0] [111:95] out6 = out;
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wire [15:0] [127:111] out7 = out;
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wire [15:0] [143:127] out8 = out;
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wire [15:0] [159:143] out9 = out;
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wire [15:0] [179:159] out10 = out;
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wire [15:0] [191:179] out11 = out;
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wire [15:0] [207:191] out12 = out;
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wire [15:0] [223:207] out13 = out;
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wire [15:0] [239:223] out14 = out;
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wire [15:0] [255:239] out15 = out;
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wire [15:0] [271:255] out16 = out;
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wire [15:0] [287:271] out17 = out;
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wire [15:0] [303:287] out18 = out;
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wire [15:0] [319:303] out19 = out;
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wire [15:0] [335:319] out20 = out;
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wire [15:0] [351:335] out21 = out;
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wire [15:0] [367:351] out22 = out;
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wire [15:0] [383:367] out23 = out;
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wire [15:0] [399:383] out24 = out;
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wire [15:0] [415:399] out25 = out;
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wire [15:0] [431:415] out26 = out;
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wire [15:0] [447:431] out27 = out;
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wire [15:0] [463:447] out28 = out;
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wire [15:0] [479:463] out29 = out;
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wire [15:0] [495:479] out30 = out;
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wire [15:0] [511:495] out31 = out;
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endpackage |