Erick
17 lines
482 B
Verilog
17 lines
482 B
Verilog
include "predefined/and_gate.v"
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module and_tb();
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reg ta,tb;
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wire ty;
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and_gate dut(y, ta, tb);
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initial begin
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ta = 0; tb = 0;
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$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
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#5 ta = 1; tb = 0;
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$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
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#5 ta = 0; tb = 1;
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$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
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#5 ta = 1; tb = 1;
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$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
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end
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endmodule |