testbench dump

gates/testbench/and16_tb.v

@@ -0,0 +1,16 @@
+include "predefined/and16.v"
+
+module and_tb();
+    reg ta,tb;
+    wire ty;
+    and_gate dut(y, ta, tb);
+        initial begin
+            ta = 0'b16;
+            tb = 0'b16;
+            i=0
+            for(i<=15, i=i+1)
+                $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+                ta = ta+1;
+                tb = tb+1;
+        end
+endmodule

gates/testbench/and_tb.v

@@ -1,4 +1,4 @@
-include "and_gate.v"
+include "predefined/and_gate.v"
 
 module and_tb();
     reg ta,tb;

gates/testbench/demux_tb.v

@@ -1,3 +1,5 @@
+include "predefined/demux.v"
+
 module demux_tb();
     reg a,b, sel;
     output y;

gates/testbench/mux_tb.v

@@ -1,4 +1,4 @@
-include "mux.v"
+include "predefined/mux.v"
 
 module mux_tb();
     reg a,b, sel;

gates/testbench/nand_tb.v

@@ -1,4 +1,4 @@
-include "nand_gate.v"
+include "predefined/nand_gate.v"
 
 module nand_tb();
     reg ta,tb;

gates/testbench/nor_tb.v

@@ -0,0 +1,18 @@
+include "predefined/nor_gate.v"
+
+module nor_tb();
+    reg ta, tb;
+    wire ty;
+
+    nor_gate dut(y, ta, tb);
+
+    initial begin
+        ta=0, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=0, tb=1;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=1;
+    end
+endmodule

gates/testbench/not_tb.v

@@ -1,4 +1,4 @@
-include "not_gate.v"
+include "predefined/not_gate.v"
 
 module not_tb();
     reg ta;

gates/testbench/or_tb.v

@@ -1,4 +1,4 @@
-include "or_gate.v"
+include "predefined/or_gate.v"
 
 module or_tb();
     reg ta, tb;

gates/testbench/xnor_tb.v

@@ -0,0 +1,18 @@
+include "predefined/xnor_gate.v"
+
+module xnor_tb();
+    reg ta, tb;
+    wire ty;
+
+    xnor_gate dut(y, ta, tb);
+
+    initial begin
+        ta=0, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=0, tb=1;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=1;
+    end
+endmodule

gates/testbench/xor_tb.v

@@ -0,0 +1,18 @@
+include "predefined/nor_gate.v"
+
+module nor_tb();
+    reg ta, tb;
+    wire ty;
+
+    nor_gate dut(y, ta, tb);
+
+    initial begin
+        ta=0, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=0, tb=1;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=1;
+    end
+endmodule