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iceberg/gates/predefined/nor_gate.v
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2022-02-22 13:06:51 +01:00

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Verilog

include "or_gate.v"
include "not_gate.v"
module nor_gate(a, b, y);
input a, b;
output y;
logic sel;
always @ (a or b)begin
or_gate(a, b, sel);
not_gate(sel, y);
end
endmodule