created predefined gates in verilog

gates/predefined/and_gate.v

@@ -0,0 +1,12 @@
+module and_gate(a, b, y);
+    input a, b;
+    output y;
+
+    always @ (a or b)begin
+        if(a==1'b1 and b==1'b1)begin
+            y=1'b1;
+        end
+        else
+            y=0'b0;
+    end
+endmodule

gates/predefined/nor_gate.v

@@ -0,0 +1,13 @@
+include "or_gate.v"
+include "not_gate.v"
+
+module nor_gate(a, b, y);
+    input a, b;
+    output y;
+    logic sel;
+
+    always @ (a or b)begin
+        or_gate(a, b, sel);
+        not_gate(sel, y);
+    end
+endmodule

gates/predefined/not_gate.v

@@ -0,0 +1,12 @@
+module not_gate(a, y);
+    input a;
+    output y;
+
+    always @ (a)begin
+        if(a==1'b1)begin
+            y=0'b0;
+        end
+        else
+            y=1'b1;
+    end
+endmodule

gates/predefined/or_gate.v

@@ -0,0 +1,12 @@
+module or_gate(a, b, y);
+    input a, b;
+    output y;
+
+    always @ (a or b)begin
+        if(a==0'b0 and b==0'b0)begin
+            y=0'b0;
+        end
+        else
+            y=1'b1;
+    end
+endmodule

gates/predefined/xnor_gate.v

@@ -0,0 +1,17 @@
+include "and_gate.v"
+include "xnor_gate.v"
+include "not_gate.v"
+
+module xnor_gate(a, b, y);
+    input a, b;
+    output y;
+    logic selA, selB, tmpXnorA, tmpXnorB;
+
+    always @ (a or b)begin
+        not_gate(a, selA);
+        not_gate(b, selB);
+        and_gate(a, selB, tmpXnorA)
+        and_gate(selA, b, tmpXnorB)
+        xnor_gate(tmpXnorA, tmpXnorB, y)
+    end
+endmodule

gates/predefined/xor_gate.v

@@ -0,0 +1,17 @@
+include "and_gate.v"
+include "xor_gate.v"
+include "not_gate.v"
+
+module xnor_gate(a, b, y);
+    input a, b;
+    output y;
+    logic selA, selB, tmpXorA, tmpXorB;
+
+    always @ (a or b)begin
+        not_gate(a, selA);
+        not_gate(b, selB);
+        and_gate(a, selB, tmpXnorA);
+        and_gate(selA, b, tmpXnorB);
+        xor_gate(tmpXorA, tmpXorB, y);
+    end
+endmodule

gates/testbench/and_tb.v

@@ -0,0 +1 @@
+include "gates/and.v"