eeeck/iceberg
Archived
1
0
Fork 0
Code Activity
This repository has been archived on 2026-02-06. You can view files and clone it. You cannot open issues or pull requests or push a commit.
3 Commits 3 Branches 0 Tags
2fde4d5bf5066c608cd11fe583409d04b647407f
T
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Erick 2fde4d5bf5 created predefined gates in verilog
2022-02-22 13:06:51 +01:00
gates
created predefined gates in verilog
2022-02-22 13:06:51 +01:00
.gitattributes
add git files
2022-02-22 13:06:26 +01:00
.gitignore
add git files
2022-02-22 13:06:26 +01:00
LICENSE
Initial commit
2022-02-15 00:07:24 +01:00
README.md
add git files
2022-02-22 13:06:26 +01:00

README.md

nand2tetris-project

Hack computer, built following nand2tetris course using Verilog

The gates are designed following a behavioural modelling philosophy (mostly for learning purposes, even though a data flow modelling system would be preferible for big projects)

View Git Blame Copy Permalink
S
Description
No description provided
Readme 124 KiB
Languages
SystemVerilog 45.9%
Verilog 41.3%
C 8.3%
Assembly 3.2%
V 1.3%