3 Commits

This Branch

This Branch

All Branches

Author	SHA1	Message	Date
Erick	2fde4d5bf5	created predefined gates in verilog	2022-02-22 13:06:51 +01:00
Erick	4cbdd294fb	add git files	2022-02-22 13:06:26 +01:00
Erick	63323b9bb6	Initial commit	2022-02-15 00:07:24 +01:00