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iceberg/gates/predefined/or_gate.v
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2022-02-22 13:06:51 +01:00

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Verilog

module or_gate(a, b, y);
input a, b;
output y;
always @ (a or b)begin
if(a==0'b0 and b==0'b0)begin
y=0'b0;
end
else
y=1'b1;
end
endmodule