12 lines
202 B
Verilog
12 lines
202 B
Verilog
module or_gate(a, b, y);
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input a, b;
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output y;
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always @ (a or b)begin
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if(a==0'b0 and b==0'b0)begin
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y=0'b0;
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end
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else
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y=1'b1;
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end
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endmodule |