Erick
11 lines
156 B
Systemverilog
11 lines
156 B
Systemverilog
module halfadder (
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output sum_bit,
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output carry_bit,
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input a,
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input b
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);
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xor sum_g(sum_bit, a, b);
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and carry_g(carry_bit, a, b);
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endmodule |