Erick
10 lines
194 B
Verilog
10 lines
194 B
Verilog
module mux(y, a, b, sel);
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input a, b, sel;
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output y;
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wire notSel, andA, andB;
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not(notSel, sel);
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and(andA, a, sel);
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and(andB, b, notSel);
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or(y, andA, andB);
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endmodule |