Erick
27 lines
546 B
Verilog
27 lines
546 B
Verilog
'include "and16.v"
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'include "not16.v"
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'include "or4way.v"
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module mux4way16(out, i0, i1, i2, i3, sel);
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input [15:0]i0;
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input [15:0]i1;
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input [15:0]i2;
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input [15:0]i3;
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input [1:0]sel;
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output [15:0]out;
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wire [15:0]tmp0;
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wire [15:0]tmp1;
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wire [15:0]tmp2;
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wire [15:0]tmp3;
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wire [2:0] [15:0] sel16 = sel;
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not16(notSel16, sel16);
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and16(tmp0, i0, notSel16);
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and16(tmp1, i1, sel16);
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and16(tmp2, i2, notSel16);
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and16(tmp3, i3, sel16);
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or4way16(out, tmp0, tmp1, tmp2, tmp3);
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endmodule |