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iceberg/gates/or4way.v
T
2022-03-01 23:35:17 +01:00

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Verilog

module or4way(out, i0, i1, i2, i3);
input i0, i1, i2, i3;
output [3:0]out;
wire tmp01, tmp23,;
or(tmp01, i0, i1);
or(tmp23, i2, i3);
or(out, tmp01, tmp23);
endmodule