Erick
14 lines
269 B
Verilog
14 lines
269 B
Verilog
module or4way16(out, i0, i1, i2, i3);
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input [15:0]i0;
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input [15:0]i1;
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input [15:0]i2;
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input [15:0]i3;
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output [15:0]out;
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wire [15:0]tmp01;
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wire [15:0]tmp23,;
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or(tmp01, i0, i1);
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or(tmp23, i2, i3);
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or(out, tmp01, tmp23);
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endmodule |