Erick
11 lines
256 B
Verilog
11 lines
256 B
Verilog
'include "or4way.v"
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module or8way(out4, i0, i1, i2, i3, i4, i5, i6, i7);
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input i0, i1, i2, i3, i4, i5, i6, i7;
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output out;
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wire tmp0, tmp1;
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or4way(tmp0, i0, i1, i2, i3);
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or4way(tmp1, i4, i5, i6, i7);
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or(out, tmp0, tmp1);
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endmodule |