Erick
15 lines
240 B
Verilog
15 lines
240 B
Verilog
include "not_gate.v"
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module not_tb();
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reg ta;
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wire ty;
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not_gate dut(y, ta);
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initial begin
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ta=0;
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$monitor("IN: %b", ta, "OUT: ", y)
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ta=1;
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$monitor("IN: %b", ta, "OUT: ", y)
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end
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endmodule |