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iceberg/cpu/alu/halfadder.sv
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Erick f78cc40524 create ALU
added files:
halfadder.sv
adder.sv
adder16.sv
alu.sv
2022-03-05 00:00:16 +01:00

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Systemverilog

package halfadder (
output sum_bit,
output carry_bit,
input a,
input b
);
xor sum_g(sum_bit, a, b);
and carry_g(carry_bit, a, b);
endpackage