Erick
29 lines
652 B
Verilog
29 lines
652 B
Verilog
'include "and16.v"
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module and8way16(out, i0, i1, i2, i3, i4, i5, i6, i7);
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input [15:0]i0;
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input [15:0]i1;
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input [15:0]i2;
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input [15:0]i3;
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input [15:0]i4;
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input [15:0]i5;
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input [15:0]i6;
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input [15:0]i7;
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output [15:0]out;
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wire [15:0]tmp01;
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wire [15:0]tmp23;
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wire [15:0]tmp45;
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wire [15:0]tmp67;
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wire [15:0]tmp0123;
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wire [15:0]tmp4567;
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and16 andA(tmp01, i0, i1);
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and16 andB(tmp23, i2, i3);
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and16 andC(tmp45, i4, i5);
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and16 andD(tmp67, i6, i7);
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and16 andAB(tmp0123, tmp01, tmp23);
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and16 andCD(tmp4567, tmp45, tmp67);
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and16 andFinal(out, tmp0123, tmp4567);
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endmodule |