Erick
21 lines
491 B
Verilog
21 lines
491 B
Verilog
module not16(y16, a16);
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input [15:0] a16;
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output [15:0] y16;
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not(y16[0], a16[0]);
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not(y16[1], a16[1]);
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not(y16[2], a16[2]);
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not(y16[3], a16[3]);
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not(y16[4], a16[4]);
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not(y16[5], a16[5]);
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not(y16[6], a16[6]);
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not(y16[7], a16[7]);
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not(y16[8], a16[8]);
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not(y16[9], a16[9]);
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not(y16[10], a16[10]);
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not(y16[11], a16[11]);
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not(y16[12], a16[12]);
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not(y16[13], a16[13]);
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not(y16[14], a16[14]);
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not(y16[15], a16[15]);
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endmodule |