Erick
27 lines
397 B
Systemverilog
27 lines
397 B
Systemverilog
import d_flipflop::*;
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`include "not16.v"
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package pc (
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input [15:0]in;
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input load;
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input inc;
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input reset;
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input clk;
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output [15:0]out;
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);
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wire [15:0] zero16 = 15'b0000000000000000;
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wire [15:0] one16 = 15'b0000000000000001;
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if (reset == 1)
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out = zero16;
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else if (load == 1)
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out = in;
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else if (inc == 1)
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out = out + one16;
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else
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out = out;
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end
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endpackage |