eeeck/il-clock
Archived
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Update comments and whitespace

Browse Source
This commit is contained in:
Erick
2026-01-09 12:30:00 +01:00
parent 0028500ffe
commit 12a61f1327
2 changed files with 9 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/clockinator.S
+2 -2
View File
@@ -11,7 +11,7 @@
.org 0x0002 ; INT0 button interrupt (tap tempo)
;rjump tap_tempo --> should have timer0_start --> if timer0_overflow_count=0 start timer (?)
.org 0x0004 ; TIMER0 overflow
rjmp timer0_isr
rjmp timer0_isr
.org 0x0006 ; TIMER1_COMPA
rjmp timer1_isr
@@ -46,7 +46,7 @@ main:
;ldi r26, 60 ; Default BPM //TODO: save to eeprom not register, on runtime also ldi on r24 register
; Setup general registers
; Setup general registers and global variables
; 0
clr r0
sts timer0_overflow_count, r0
src/timer.inc
+7 -8
View File
@@ -17,14 +17,14 @@ timer0_set:
timer0_start:
ldi r16, (1<<CS02) | (1<<CS00)
out TCCR0B, r16 ; Load prescaler = 1024
out TCCR0B, r16 ; Load prescaler (00000101 = 1024)
ret
timer0_isr:
lds r16, timer0_overflow_count
cpi r16, 160 ; Max count for min BPM<=24 (slightly lower)
brge .timer0_stop
cpi r16, 160 ; BPM update timeframe expiration limit (160 -> ~20 BPM)
brge .timer0_stop ;//TODO: check if breq would be more efficient than brge
add r16, r1
sts timer0_overflow_count, r16 ; Update new overflow counter
@@ -32,15 +32,15 @@ timer0_isr:
reti
.timer0_stop:
sts timer0_overflow_count, r0 ; Reset overflow byte
out TCCR0B, r0 ; Stop timer0 by clearing prescaler
sts timer0_overflow_count, r0 ; Reset overflow byte
out TCCR0B, r0 ; Stop timer0 by clearing prescaler
ldi r16, (1 << TOV0)
out TIFR, r16 ; Clear timer0 overflow flag register
out TIFR, r16 ; Clear timer0 overflow flag register
reti
timer1_set:
ldi r19, 127 ; Timer base period (time granularity)
out OCR1A, r19 ; Set timer count compare
@@ -56,7 +56,6 @@ timer1_set:
ret
; ISR
timer1_isr:
in r21, SREG
push r21