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Update timer0 logic for tap tempo with overflow counter. Update timer1

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setup
This commit is contained in:
Erick
2026-01-09 11:40:14 +01:00
parent a6376aa7ab
commit 8205c7892a
1 changed files with 43 additions and 7 deletions
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src/timer.inc
+43 -7
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@@ -2,16 +2,52 @@
; r16: timer0 setup (can reuse after ret)
; r17: timer1 dynamic setup (always needed)
; Timer0 (static, low precision)
timer0_set:
ldi r16, (1 << WGM01) ; Write CTC (Clear Timer on Compare) to 1
out TCCR0A, r16 ; On T/C Control Register A enable CTC waveform
out TCCR0A, r0 ; T/C Control Register A enable normal mode
ldi r16, 244 ; Load counter target limit value (ticks)
out OCR0A, r16 ; Load target for compatison with TCNT0
ldi r16, (1 << TOIE0)
out TIMSK, r16 ; Enable Timer0 overflow
ldi r16, (1 << OCIE0A) ; Write Compare Match A Interrupt Enable to 1
out TIMSK, r16 ; Allow Timer0 to interrupt
ret
timer0_start:
ldi r16, (1<<CS02) | (1<<CS00)
out TCCR0B, r16 ; Load prescaler = 1024
ret
timer0_isr:
lds r16, timer0_overflow_count
cpi r16, 160 ; Max count for min BPM<=24 (slightly lower)
brge .timer0_stop
add r16, r1
sts timer0_overflow_count, r16 ; Update new overflow counter
reti
.timer0_stop
sts timer0_overflow_count, r0 ; Reset overflow byte
out TCCR0B, r0 ; Stop timer0 by clearing prescaler
ldi r16, (1 << TOV0)
out TIFR, r16 ; Clear timer0 overflow flag register
reti
timer1_set:
ldi r19, 127 ; Timer base period (time granularity)
out OCR1A, r19 ; Set timer count compare
; BPM safe range: 24~255
; CTC1: Enable CTC mode, CS12|CS11 (Bits 2,1): Prescaler 32 (0110)
ldi r20, (1<<CTC1) | (1<<CS12) | (1<<CS11)
out TCCR1, r20 ; Load prescaler
in r20, TIMSK ; Read current interrupt mask
ori r20, (1<<OCIE1A)
out TIMSK, r20 ; Enable compare match interrupt
ret