Update timer1 ISR logic with overflow counter and accumulator
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+27
-14
@@ -15,18 +15,31 @@ timer0_set:
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ret
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; Timer1 will be dynamically changed in main (tempo)
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;timer1_set:
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; Load 10011011 to register:
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; CTC1 (Bit 7): Reset timer to 0 when it matches OCR1C
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; COM1A0 (Bit 4): Toggle OC1A (PB1) when it matches OCR1A
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; CS13, CS11, CS10 (Bits 3,1,0): Prescaler 1024 (1011)
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; ldi r17, (1 << CTC1) | (1 << COM1A0) | (1 << CS13) | (1 << CS11) | (1 << CS10)
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; out TCCR1, r16 ; On T/C Control Register 1, enable: CTC1 COM1A0 CS13 CS11 CS10
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.MACRO SET_BPM target_high, target_low
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ldi r20, \target_high
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ldi r19, \target_low
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.endm
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;timer1_use:
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; ldi r17, 256 ; Load counter total value (ticks)
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; ldi r17, 5 ; Load counter on value (ticks)
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; //TODO: change r17 on main and then call timer1_dyn to use the value already on r16 (so its dynamic)
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; out OCR1C, r17 ; Compare target to current counter (frequency)
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; out OCR1A, r17 ; Compare target to current counter (phase shift)
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; ISR
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timer1_isr:
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in r21, SREG
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push r21
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ldi r21, 255 ; Phase increment (quantization)
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add r17, r21 ; Add low byte to accumulator
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adc r18, r1 ; Add high byte to accumulator
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cp r18, r20 ; Compare HB accumulator vs HB target
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cpc r17, r19 ; Compare LB accumulator vs LB target
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brlo .exit ; Exit if accumulator < target
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;rjump send_midi (rjump or macro, let's see later...)
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; To correct any overshoot of acc:
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sub r17, r19 ; Subtract LB target from LB accumulator
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sbc r18, r20 ; Subtract HB target from HB accumulator
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.exit:
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pop r21
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out SREG, r21
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reti
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