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Update timer1 ISR logic with overflow counter and accumulator

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This commit is contained in:
Erick
2026-01-09 11:39:30 +01:00
parent 7b70962159
commit a6376aa7ab
1 changed files with 27 additions and 14 deletions
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src/timer.inc
+27 -14
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@@ -15,18 +15,31 @@ timer0_set:
ret ret
; Timer1 will be dynamically changed in main (tempo) .MACRO SET_BPM target_high, target_low
;timer1_set: ldi r20, \target_high
; Load 10011011 to register: ldi r19, \target_low
; CTC1 (Bit 7): Reset timer to 0 when it matches OCR1C .endm
; COM1A0 (Bit 4): Toggle OC1A (PB1) when it matches OCR1A
; CS13, CS11, CS10 (Bits 3,1,0): Prescaler 1024 (1011)
; ldi r17, (1 << CTC1) | (1 << COM1A0) | (1 << CS13) | (1 << CS11) | (1 << CS10)
; out TCCR1, r16 ; On T/C Control Register 1, enable: CTC1 COM1A0 CS13 CS11 CS10
;timer1_use: ; ISR
; ldi r17, 256 ; Load counter total value (ticks) timer1_isr:
; ldi r17, 5 ; Load counter on value (ticks) in r21, SREG
; //TODO: change r17 on main and then call timer1_dyn to use the value already on r16 (so its dynamic) push r21
; out OCR1C, r17 ; Compare target to current counter (frequency)
; out OCR1A, r17 ; Compare target to current counter (phase shift) ldi r21, 255 ; Phase increment (quantization)
add r17, r21 ; Add low byte to accumulator
adc r18, r1 ; Add high byte to accumulator
cp r18, r20 ; Compare HB accumulator vs HB target
cpc r17, r19 ; Compare LB accumulator vs LB target
brlo .exit ; Exit if accumulator < target
;rjump send_midi (rjump or macro, let's see later...)
; To correct any overshoot of acc:
sub r17, r19 ; Subtract LB target from LB accumulator
sbc r18, r20 ; Subtract HB target from HB accumulator
.exit:
pop r21
out SREG, r21
reti