Added options to specify dimension ordering
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+31
-3
@@ -7,6 +7,12 @@
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namespace tk { namespace dnn {
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enum dimFormat_t {
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CHW,
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NCHW,
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//NHWC
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};
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/**
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Data representation between layers
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n = batch size
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@@ -21,9 +27,31 @@ struct dataDim_t {
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dataDim_t() : n(1), c(1), h(1), w(1), l(1) {};
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dataDim_t(nvinfer1::Dims &d) :
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n(1), c(d.d[0] ? d.d[0] : 1), h(d.d[1] ? d.d[1] : 1),
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w(d.d[2] ? d.d[2] : 1), l(d.d[3] ? d.d[3] : 1) {};
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dataDim_t(nvinfer1::Dims &d, dimFormat_t df) {
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switch(df) {
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case CHW:
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n=1;
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c = d.d[0] ? d.d[0] : 1;
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h = d.d[1] ? d.d[1] : 1;
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w = d.d[2] ? d.d[2] : 1;
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l = d.d[3] ? d.d[3] : 1;
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break;
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case NCHW:
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n = d.d[0] ? d.d[0] : 1;
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c = d.d[1] ? d.d[1] : 1;
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h = d.d[2] ? d.d[2] : 1;
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w = d.d[3] ? d.d[3] : 1;
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l = d.d[4] ? d.d[4] : 1;
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break;
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// case NHWC:
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// n = d.d[0] ? d.d[0] : 1;
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// h = d.d[1] ? d.d[1] : 1;
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// w = d.d[2] ? d.d[2] : 1;
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// c = d.d[3] ? d.d[3] : 1;
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// l = d.d[4] ? d.d[4] : 1;
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// break;
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}
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};
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dataDim_t(int _n, int _c, int _h, int _w, int _l = 1) :
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n(_n), c(_c), h(_h), w(_w), l(_l) {};
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@@ -73,7 +73,7 @@ public:
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PluginFactory *pluginFactory;
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NetworkRT(Network *net, const char *name, const char *input_name="data", const char *output_name="out");
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NetworkRT(Network *net, const char *name, dimFormat_t dim_format=CHW, const char *input_name="data", const char *output_name="out");
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virtual ~NetworkRT();
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int getMaxBatchSize() {
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+4
-4
@@ -26,7 +26,7 @@ namespace tk { namespace dnn {
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std::map<Layer*, nvinfer1::ITensor*>tensors;
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NetworkRT::NetworkRT(Network *net, const char *name, const char *input_name, const char *output_name) {
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NetworkRT::NetworkRT(Network *net, const char *name, dimFormat_t dim_format, const char *input_name, const char *output_name) {
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float rt_ver = float(NV_TENSORRT_MAJOR) +
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float(NV_TENSORRT_MINOR)/10 +
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@@ -167,17 +167,17 @@ NetworkRT::NetworkRT(Network *net, const char *name, const char *input_name, con
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Dims iDim = engineRT->getBindingDimensions(buf_input_idx);
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input_dim = dataDim_t(iDim);
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input_dim = dataDim_t(iDim, dim_format);
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input_dim.print();
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Dims oDim = engineRT->getBindingDimensions(buf_output_idx);
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output_dim = dataDim_t(oDim);
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output_dim = dataDim_t(oDim, dim_format);
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output_dim.print();
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// create GPU buffers and a stream
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for(int i=0; i<engineRT->getNbBindings(); i++) {
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Dims dim = engineRT->getBindingDimensions(i);
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buffersDIM[i] = dataDim_t(dim);
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buffersDIM[i] = dataDim_t(dim, dim_format);
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std::cout<<"RtBuffer "<<i<<" dim: "; buffersDIM[i].print();
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checkCuda(cudaMalloc(&buffersRT[i], engineRT->getMaxBatchSize()*buffersDIM[i].tot()*sizeof(dnnType)));
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}
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