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minor fixes

This commit is contained in:
Erick
2022-03-27 19:00:14 +02:00
parent e568e64264
commit 09676ffb82
2 changed files with 12 additions and 8 deletions
+10 -6
View File
@@ -4,27 +4,31 @@ import reg16::*
'include "gates/mux16.v"
package cpu (
module cpu (
input [15:0]inM,
input [15:0]instr,
input reset,
input clk,
input sel[15:0]
output [15:0]outM,
output flagM[2:0]
output [2:0]flagM
output wrtM,
output [15:0]addrM,
output [15:0]pc
);
wire [11:6] [5:0] addrM = sel;
//FIXME: wrtM is not defined!
not (wrtM, notWrtM); //TODO: verify this
mux16 instrMux(outInstrMux, outM, instr, wrtM);
reg16 AReg(outInstrMux, wrtM, clk, addrM notOutAReg);
reg16 AReg(outInstrMux, wrtM, clk, addrM, notOutAReg);
mux16 inputMux(InAlu1, addrM, inM, wrtM);
reg16 DReg(outM, wrtM, clk, InAlu0, notOut);
reg16 DReg(outM, notWrtM, clk, InAlu0, notOut);
alu alu(InAlu0, InAlu1, sel, outM, flagM);
pc pc(addrM, wrtM, reset, clk, pc);
endpackage
endmodule
+2 -2
View File
@@ -1,6 +1,6 @@
import ram4096::*;
package ram16384 (
module ram16384 (
input [16384:0]in;
input [13:0]addr;
input load;
@@ -31,4 +31,4 @@ wire [4095:0] [8191:4095] out1 = out;
wire [4095:0] [12287:8191] out2 = out;
wire [4095:0] [16383:12287] out3 = out;
endpackage
endmodule