minor fixes
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+10
-6
@@ -4,27 +4,31 @@ import reg16::*
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'include "gates/mux16.v"
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package cpu (
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module cpu (
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input [15:0]inM,
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input [15:0]instr,
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input reset,
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input clk,
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input sel[15:0]
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output [15:0]outM,
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output flagM[2:0]
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output [2:0]flagM
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output wrtM,
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output [15:0]addrM,
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output [15:0]pc
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);
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wire [11:6] [5:0] addrM = sel;
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//FIXME: wrtM is not defined!
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not (wrtM, notWrtM); //TODO: verify this
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mux16 instrMux(outInstrMux, outM, instr, wrtM);
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reg16 AReg(outInstrMux, wrtM, clk, addrM notOutAReg);
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reg16 AReg(outInstrMux, wrtM, clk, addrM, notOutAReg);
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mux16 inputMux(InAlu1, addrM, inM, wrtM);
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reg16 DReg(outM, wrtM, clk, InAlu0, notOut);
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reg16 DReg(outM, notWrtM, clk, InAlu0, notOut);
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alu alu(InAlu0, InAlu1, sel, outM, flagM);
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pc pc(addrM, wrtM, reset, clk, pc);
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endpackage
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endmodule
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@@ -1,6 +1,6 @@
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import ram4096::*;
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package ram16384 (
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module ram16384 (
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input [16384:0]in;
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input [13:0]addr;
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input load;
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@@ -31,4 +31,4 @@ wire [4095:0] [8191:4095] out1 = out;
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wire [4095:0] [12287:8191] out2 = out;
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wire [4095:0] [16383:12287] out3 = out;
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endpackage
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endmodule
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