eeeck/iceberg
Archived
1
0
Fork 0
Code Activity

created predefined gates in verilog

Browse Source
This commit is contained in:
Erick
2022-02-22 13:06:51 +01:00
parent 4cbdd294fb
commit 2fde4d5bf5
7 changed files with 84 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
gates/testbench/and_tb.v
+1
View File
@@ -0,0 +1 @@
include "gates/and.v"