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# Square One - From logic gates to 16-bit OS
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Square One is a virtual computer built from scratch, starting from the logic gates and CPU to an assembler and compiler, whilst at the very high level Java is implemented-
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Square One is a virtual computer built from scratch, built starting from the logic gates and CPU to an assembler and compiler, whilst at the very high level Java is implemented.
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## Architecture
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Ex: a 4-way mux gate:
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'''
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'''v
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module mux4way(out, i0, i1, i2, i3, sel0, sel1);
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input i0, i1, i2, i3;
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input [3:0]sel;
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and(tmp3, i3, sel1);
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or4way(out, tmp0, tmp1, tmp2, tmp3);
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endmodule
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'''
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#### Predefined gates (path: /gates/predefined)
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The predefined gates are by default implemented on Verilog/Systemverilog. Thus they are not strictly needed for building more advanced gates or chipset, but I still decided to add them as reference and learning purposes.
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#### Testbenches (path: /testbenches)
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Testbenches are a way to test the implementation of a particular gate using a Verilog compiler. They output a set of I/O command to test the correct implementation of a given gate.
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### Processor (path: /cpu)
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### Arithmetic Logic Unit (path: /alu)
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#### Arithmetic Logic Unit (path: /cpu/alu)
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The ALU is written is Systemverilog (such as the CPU and other complex components). It handles two 16-bit inputs, a 6-bit opcode and a 16-bit output and a 2-bit sign flag. It computes the following instructions:
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x+y
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@@ -86,6 +82,10 @@ And the 2-bit sign flag is:
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1 (if output = 0)
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2 (if output > 0)
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## Testbenches (path: /testbenches)
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Testbenches are a way to test the implementation of a particular gate using a Verilog compiler. They output a set of I/O command to test the correct implementation of a given gate.
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## Usage
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#### Verilog/Systemverilog logic gates
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To run any Verilog (.v) or Systemverilog (.sv) file, use *iverilog* (available for Windows, Linux and MacOS) using the command:
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