typo

gates/and8way.v

@@ -6,7 +6,7 @@ module and8way(out, i0, i1, i2, i3, i4, i5, i6, i7);
     and(tmp01, i0, i1);
     and(tmp23, i2, i3);
     and(tmp45, i4, i5);
-    and(tmp67, i6, i17);
+    and(tmp67, i6, i7);
 
     and(tmp0123, tmp01, tmp23);
     and(tmp4567, tmp45, tmp67);

gates/nand16.v

@@ -1,4 +1,4 @@
-module band16(y16, a16, b16);
+module nand16(y16, a16, b16);
     input [15:0]a16;
     input[15:0]b16;
     output [15:0]y16;