created sr, jk and data flipflops

memory/flipflop/d_flipflop.sv

@@ -0,0 +1,15 @@
+'include "gates/nand3way16.v"
+
+import sr_flipflop::*;
+
+package d_flipflop (
+    output [15:0]dq, [15:0]dq_compl
+    input [15:0]d, clk,
+);
+
+nand16(tmp0, d, clk);
+nand16(tmp1, clk, tmp0);
+
+sr_flipflop(dq, dq_compl, tmp0, tmp1);
+
+endpackage

memory/flipflop/jk_flipflop.sv

@@ -0,0 +1,15 @@
+'include "gates/nand3way16.v"
+
+import sr_flipflop::*;
+
+package jk_flipflop (
+    output [15:0]jkq, [15:0]jkq_compl
+    input [15:0]j, [15:0]k, [15:0]clk   //FIXME: is 26bit clock correct? Like can it go only as 0000000000000000 and 1111111111111111?
+);
+
+nand3way16(notS, jkq_compl, j, clk);
+nand3way16(notR, jkq, k, clk);
+
+sr_flipflop(jkq, jkq_compl, notS, notR);
+
+endpackage

memory/flipflop/sr_flipflop.sv

@@ -0,0 +1,11 @@
+'include "gates/nand16.v"
+
+package sr_flipflop (
+    output [15:0]srq, [15:0]srq_compl
+    input [15:0]s, [15:0]r
+);
+
+nand16 nand0(q, s, q_compl);
+nand16 nand1(q_compl, r, q);
+
+endpackage

memory/sr_flipflop.sv

@@ -1,13 +0,0 @@
-'include "gates/nand16.v"
-
-module sr_flipflop (
-    input s, r, clk,
-    output q, q_compl
-);
-
-nand16 nand0(tmp0, s, clk);
-nand16 nand1(tmp1, r, clk);
-nand16 nand2(q, tmp0, q_compl);
-nand16 nand3(q_compl, tmp1, q);
-
-endmodule