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Erick
2022-03-05 00:02:05 +01:00
parent f78cc40524
commit ba2cc09b0c
1 changed files with 19 additions and 18 deletions
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README.md
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@@ -8,9 +8,7 @@ Logic gates are the lowest level point from which this project is implemented. T
Most of the gates also have a 16-bit version and eventually a n-way version (some even n-way-16-bit). Most of the gates also have a 16-bit version and eventually a n-way version (some even n-way-16-bit).
Ex: a 4-way mux gate: Ex: a 4-way mux gate:
'''
include "mux.v"
include "or4way.v"
module mux4way(out, i0, i1, i2, i3, sel0, sel1); module mux4way(out, i0, i1, i2, i3, sel0, sel1);
input i0, i1, i2, i3; input i0, i1, i2, i3;
@@ -33,6 +31,7 @@ Ex: a 4-way mux gate:
endmodule endmodule
'''
#### Predefined gates (path: /gates/predefined) #### Predefined gates (path: /gates/predefined)
The predefined gates are by default implemented on Verilog/Systemverilog. Thus they are not strictly needed for building more advanced gates or chipset, but I still decided to add them as reference and learning purposes. The predefined gates are by default implemented on Verilog/Systemverilog. Thus they are not strictly needed for building more advanced gates or chipset, but I still decided to add them as reference and learning purposes.
@@ -42,6 +41,7 @@ Testbenches are a way to test the implementation of a particular gate using a Ve
Ex: testbench for a xor gate: Ex: testbench for a xor gate:
''' '''
module xor_tb(); module xor_tb();
reg ta, tb; reg ta, tb;
wire ty; wire ty;
@@ -58,6 +58,7 @@ module xor_tb();
ta=1, tb=1; ta=1, tb=1;
end end
endmodule endmodule
''' '''
### Arithmetic Logic Unit (path: /alu) ### Arithmetic Logic Unit (path: /alu)