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Erick
2022-03-07 02:58:47 +01:00
parent 42705d8f17
commit d3a9f400e2
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README.md
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@@ -10,25 +10,25 @@ Most of the gates also have a 16-bit version and eventually a n-way version (som
Ex: a 4-way mux gate:
'''v
module mux4way(out, i0, i1, i2, i3, sel0, sel1);
input i0, i1, i2, i3;
input [3:0]sel;
output [3:0]out;
wire tmp0, tmp1, tmp2, tmp3;
module mux4way(out, i0, i1, i2, i3, sel0, sel1);
input i0, i1, i2, i3;
input [3:0]sel;
output [3:0]out;
wire tmp0, tmp1, tmp2, tmp3;
wire [3:0] [1:0] sel0 = sel;
wire [0:3] [1:0] sel1 = sel;
wire [3:0] [1:0] sel0 = sel;
wire [0:3] [1:0] sel1 = sel;
not(notSel0, sel0);
not(notSel1, sel1);
not(notSel0, sel0);
not(notSel1, sel1);
and(tmp0, i0, notSel0);
and(tmp1, i1, sel0);
and(tmp2, i2, notSel1);
and(tmp3, i3, sel1);
and(tmp0, i0, notSel0);
and(tmp1, i1, sel0);
and(tmp2, i2, notSel1);
and(tmp3, i3, sel1);
or4way(out, tmp0, tmp1, tmp2, tmp3);
endmodule
or4way(out, tmp0, tmp1, tmp2, tmp3);
endmodule
'''
#### Predefined gates (path: /gates/predefined)