Erick
11 lines
168 B
Verilog
11 lines
168 B
Verilog
include "or_gate.v"
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include "not_gate.v"
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module nor_gate(y, a, b);
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input a, b;
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output y;
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wire sel;
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or_gate(a, b, sel);
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not_gate(sel, y);
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endmodule |