Erick
10 lines
601 B
Markdown
10 lines
601 B
Markdown
## Gates
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Logic gates are the lowest level from which this project will be implemented.
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There are different gates, most of which also have a 16-bit version and eventually a n-way version (even in 16-bit).
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All the logic gates are written in Verilog
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### Predefined gates
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The predefined gates are by default implemented on Verilog/Systemverilog. Thus they are not strictly needed for building more advanced gates or chipset, but I still decided to add them as reference and learning purposes.
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### Testbenches
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Testbenches are a way to test the implementation of a particular gate using a Verilog compiler |