Create README.md

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+## Gates
+Logic gates are the lowest level from which this project will be implemented.
+There are different gates, most of which also have a 16-bit version and eventually a n-way version (even in 16-bit).
+All the logic gates are written in Verilog
+
+### Predefined gates
+The predefined gates are by default implemented on Verilog/Systemverilog. Thus they are not strictly needed for building more advanced gates or chipset, but I still decided to add them as reference and learning purposes.
+
+### Testbenches
+Testbenches are a way to test the implementation of a particular gate using a Verilog compiler