Erick
103 lines
3.3 KiB
Markdown
103 lines
3.3 KiB
Markdown
# Square One - From logic gates to 16-bit OS
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Square One is a virtual computer built from scratch, built starting from the logic gates and CPU to an assembler and compiler, whilst at the very high level Java is implemented.
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## Architecture
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### Logic Gates (path: /gates)
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Logic gates are the lowest level point from which this project is implemented. They are written in Verilog and then simulated using iverilog on a dedicated testbench, and any FPGA simulator will actually work. See Resources for an online 16-bit FPGA simulator.
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Most of the gates also have a 16-bit version and eventually a n-way version (some even n-way-16-bit).
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Ex: a 4-way mux gate:
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'''
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module mux4way(out, i0, i1, i2, i3, sel0, sel1);
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input i0, i1, i2, i3;
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input [3:0]sel;
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output [3:0]out;
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wire tmp0, tmp1, tmp2, tmp3;
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wire [3:0] [1:0] sel0 = sel;
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wire [0:3] [1:0] sel1 = sel;
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not(notSel0, sel0);
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not(notSel1, sel1);
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and(tmp0, i0, notSel0);
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and(tmp1, i1, sel0);
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and(tmp2, i2, notSel1);
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and(tmp3, i3, sel1);
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or4way(out, tmp0, tmp1, tmp2, tmp3);
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endmodule
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'''
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#### Predefined gates (path: /gates/predefined)
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The predefined gates are by default implemented on Verilog/Systemverilog. Thus they are not strictly needed for building more advanced gates or chipset, but I still decided to add them as reference and learning purposes.
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### Processor (path: /cpu)
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#### Arithmetic Logic Unit (path: /cpu/alu)
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The ALU is written is Systemverilog (such as the CPU and other complex components). It handles two 16-bit inputs, a 6-bit opcode and a 16-bit output and a 2-bit sign flag. It computes the following instructions:
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x+y
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x-y
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y-x
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0
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1
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-1
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x
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y
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-x
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-y
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!x
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!y
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x+1
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y+1
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x-1
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y-1
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x&y
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x|y
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The 6-bit opcode gets divided in single bits and refered to as:
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za
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na
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zb
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nb
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f
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no
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The ALU logic manipulates the a and b inputs and operates on the resulting values, and in the exact order as it follows, thus permitting to make all of the 16 operations described before:
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* if (za == 1) set x = 0 16-bit constant
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* if (na == 1) set x = !x bitwise not
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* if (zb == 1) set y = 0 16-bit constant
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* if (nb == 1) set y = !y bitwise not
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* if (f == 1) set out = x + y integer 2's complement addition
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* if (f == 0) set out = x & y bitwise and
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* if (no == 1) set out = !out bitwise not
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And the 2-bit sign flag is:
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0 (if output < 0)
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1 (if output = 0)
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2 (if output > 0)
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## Testbenches (path: /testbenches)
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Testbenches are a way to test the implementation of a particular gate using a Verilog compiler. They output a set of I/O command to test the correct implementation of a given gate.
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## Usage
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#### Verilog/Systemverilog logic gates
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To run any Verilog (.v) or Systemverilog (.sv) file, use *iverilog* (available for Windows, Linux and MacOS) using the command:
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>> iverilog filename.v
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To visually see the functioning of a gate and it's testbench you need to use *gtkwave* and have a .vcd file of the gate (plus eventually the testbench, in the same file):
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>> gtkwave filename.vcd
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## Resources
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- Online Verilog Compiler: https://www.tutorialspoint.com/compile_verilog_online.php
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- Online FPGA Simulator: https://simulator.nirajmmenon.com/ |