f78cc40524
added files: halfadder.sv adder.sv adder16.sv alu.sv
18 lines
296 B
Systemverilog
18 lines
296 B
Systemverilog
import halfadder::*;
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package adder (
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output sum_bit,
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output carry_bit,
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input a,
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input b,
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input c
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);
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halfadder halfadd(tmpXor0, tmpAnd0, a, b);
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xor sum_final(sum_bit, tmpXor0, c);
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and carry_tmp0(tmpAnd1, tmpXor0, c);
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or carry_final(carry_bit, tmpAnd0, tmpAnd1);
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endpackage |