Archived
1
0
This repository has been archived on 2026-02-06. You can view files and clone it. You cannot open issues or pull requests or push a commit.
Files
iceberg/cpu/alu/adder.sv
T
Erick f78cc40524 create ALU
added files:
halfadder.sv
adder.sv
adder16.sv
alu.sv
2022-03-05 00:00:16 +01:00

18 lines
296 B
Systemverilog

import halfadder::*;
package adder (
output sum_bit,
output carry_bit,
input a,
input b,
input c
);
halfadder halfadd(tmpXor0, tmpAnd0, a, b);
xor sum_final(sum_bit, tmpXor0, c);
and carry_tmp0(tmpAnd1, tmpXor0, c);
or carry_final(carry_bit, tmpAnd0, tmpAnd1);
endpackage