Erick
13 lines
292 B
Verilog
13 lines
292 B
Verilog
include "demux.v";
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module demux4way(out0, out1, out2, out3, i0, i1, sel);
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input i0, i1;
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input [3:0] sel;
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output out0, out1, out2, out3;
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wire [3:0] [1:0] sel0 = sel;
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wire [0:3] [1:0] sel1 = sel;
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demux(out0, out1, i0, sel0);
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demux(out2, out3, i1, sel1);
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endmodule |