Erick
19 lines
365 B
Verilog
19 lines
365 B
Verilog
include "mux.v";
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include "or4way.v";
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module mux4way(out, i0, i1, i2, i3, sel0, sel1);
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input i0, i1, i2, i3;
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input [2:0]sel;
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output [3:0]out;
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wire tmp0, tmp1, tmp2, tmp3;
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not(notSel, sel);
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and(tmp0, i0, notSel);
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and(tmp1, i1, sel);
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and(tmp2, i2, notSel);
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and(tmp3, i3, sel);
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or4way(out, tmp0, tmp1, tmp2, tmp3);
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endmodule |