Erick
24 lines
541 B
Verilog
24 lines
541 B
Verilog
include "mux4way16.v";
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include "mux16.v";
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module mux8way16(out, i0, i1, i2, i3, i4, i5, i6, i7, sel);
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input [15:0]i0;
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input [15:0]i1;
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input [15:0]i2;
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input [15:0]i3;
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input [15:0]i4;
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input [15:0]i5;
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input [15:0]i6;
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input [15:0]i7;
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input [3:0]sel;
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output [15:0]out;
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wire tmpMux1, tmpMux1;
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wire [3:0] [1:0] sel0 = sel;
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wire [0:3] [1:0] sel1 = sel;
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mux4way16(tmpMux0, i0, i1, i2, i3, sel0);
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mux4way16(tmpMux1, i4, i5, i6, i7, sel1);
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mux16(out, tmpMux0, tmpMux1, sel);
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endmodule |