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Enable timer0 interrupt

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Erick
2025-12-26 16:11:23 +01:00
parent abf11b188f
commit 29f85d29ae
1 changed files with 7 additions and 2 deletions
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src/timer.inc
+7 -2
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@@ -3,8 +3,13 @@ timer0_set:
ldi r16, (1 << WGM01) ; Load 00000010 to register (bit 1=CTC)
out TCCR0A, r16 ; On T/C Control Register A, enable CTC and
ldi r16, 244 ; Load counter target limit value (ticks)
out OCR0A, r16 ; Compare target to current counter
ldi r16, 244 ; Load counter target limit value (ticks)
out OCR0A, r16 ; Compare target to current counter
ldi r16, (1 << OCIE0A) ; Output Compare Match A Interrupt Enable
out TIMSK, r16 ; Allow Timer0 to interrupt (mask register)
ret
; Timer1 will be dynamically changed in main (tempo)
timer1_set: