Enable timer0 interrupt

2025-12-26 16:11:23 +01:00
parent abf11b188f
commit 29f85d29ae
1 changed files with 7 additions and 2 deletions
@@ -6,6 +6,11 @@ timer0_set:
    ldi     r16,        244                 ; Load counter target limit value (ticks)
    out     OCR0A,      r16                 ; Compare target to current counter

+    ldi     r16,        (1 << OCIE0A)       ; Output Compare Match A Interrupt Enable
+    out     TIMSK,      r16                 ; Allow Timer0 to interrupt (mask register)
+
+    ret
+
 ; Timer1 will be dynamically changed in main (tempo)
 timer1_set:
    ; Load 10011011 to register: