testbench dump

2022-03-01 23:35:40 +01:00
parent 0646b73f9a
commit 001b7886d6
10 changed files with 77 additions and 5 deletions
@@ -0,0 +1,16 @@
+include "predefined/and16.v"
+
+module and_tb();
+    reg ta,tb;
+    wire ty;
+    and_gate dut(y, ta, tb);
+        initial begin
+            ta = 0'b16;
+            tb = 0'b16;
+            i=0
+            for(i<=15, i=i+1)
+                $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+                ta = ta+1;
+                tb = tb+1;
+        end
+endmodule