adding testbenches

gates/testbench/mux.v

@@ -0,0 +1,32 @@
+include "mux.v"
+
+module mux_tb();
+    reg a,b, sel;
+    output y;
+    mux dut(a, b, sel, y);
+        initial begin
+            a = 0; b = 0; sel = 0;
+            $monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
+            #5;
+            a = 1; b = 0; sel = 0;
+            $monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
+            #5;
+            a = 0; b = 1; sel = 0;
+            $monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
+            #5;
+            a = 1; b = 1; sel = 0;
+            $monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
+            #5;
+            a = 0; b = 0; sel = 1;
+            $monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
+            #5;
+            a = 1; b = 0; sel = 1;
+            $monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
+            #5;
+            a = 0; b = 1; sel = 1;
+            $monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
+            #5;
+            a = 1; b = 1; sel = 1;
+            $monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
+        end
+endmodule

gates/testbench/nand_tb.v

@@ -0,0 +1,17 @@
+include "nand_gate.v"
+
+module nand_tb();
+    reg ta,tb;
+    wire ty;
+    nand_gate dut(y, ta, tb);
+        initial begin
+            ta = 0; tb = 0;
+            $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        #5  ta = 1; tb = 0;
+            $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        #5  ta = 0; tb = 1;
+            $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        #5  ta = 1; tb = 1;
+            $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        end
+endmodule

gates/testbench/not_tb.v

@@ -0,0 +1,15 @@
+include "not_gate.v"
+
+module not_tb();
+    reg ta;
+    wire ty;
+
+    not_gate dut(y, ta);
+
+    initial begin
+        ta=0;
+        $monitor("IN: %b", ta, "OUT: ", y)
+        ta=1;
+        $monitor("IN: %b", ta, "OUT: ", y)
+    end
+endmodule

gates/testbench/or_tb.v

@@ -0,0 +1,18 @@
+include "or_gate.v"
+
+module or_tb();
+    reg ta, tb;
+    wire ty;
+
+    or_gate dut(y, ta, tb);
+
+    initial begin
+        ta=0, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=0, tb=1;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=1;
+    end
+endmodule