5 Commits

Author	SHA1	Message	Date
Erick	001b7886d6	testbench dump	2022-03-01 23:35:40 +01:00
Erick	540aac9fca	add demux and testbench	2022-03-01 00:36:52 +01:00
Erick	90287bca73	adding testbenches	2022-02-28 23:55:42 +01:00
Erick	680094e4e8	verilog predefined gates (re)definition	2022-02-28 23:53:53 +01:00
Erick	2fde4d5bf5	created predefined gates in verilog	2022-02-22 13:06:51 +01:00