 Erick
|
f93143d860
|
create ram16384.sv
|
2022-03-23 13:03:58 +01:00 |
|
|
Erick
|
85fd2df83a
|
output size fix
|
2022-03-23 12:45:55 +01:00 |
|
|
Erick
|
9098b71ccc
|
fixed file name
|
2022-03-23 12:36:15 +01:00 |
|
|
Erick
|
5277d8fd78
|
name changes in ram8 chip used in ram16
|
2022-03-23 12:33:56 +01:00 |
|
|
Erick
|
c166389176
|
create ram512.sv
|
2022-03-23 12:33:22 +01:00 |
|
|
Erick
|
a52dbe03fc
|
Create ram16.sv
16-bit ram chipset
|
2022-03-22 16:47:56 +01:00 |
|
|
Erick
|
c5413708df
|
Create ram8.sv
8-bit ram chipset
|
2022-03-22 16:47:44 +01:00 |
|
|
Erick
|
3196223e02
|
create 16-bit register
|
2022-03-22 16:47:13 +01:00 |
|
|
Erick
|
5613fba905
|
minor fix
|
2022-03-22 16:46:55 +01:00 |
|
|
Erick
|
3223f3a6af
|
Create bit_reg.sv
bit_reg.v is a single bit register that uses a data flipflop
|
2022-03-08 15:08:04 +01:00 |
|
|
Erick
|
8c70d4384f
|
minor fixes in flipflop logic
|
2022-03-08 15:07:02 +01:00 |
|
|
Erick
|
b5d5fb5a05
|
created sr, jk and data flipflops
|
2022-03-08 13:54:42 +01:00 |
|
|
Erick
|
3ade6ba96a
|
create sr flipflop logic
|
2022-03-07 02:17:10 +01:00 |
|