5 Commits

Author	SHA1	Message	Date
Erick	bcb06dae6a	Create mux.v (multiplexer gate)	2022-02-28 23:56:05 +01:00
Erick	90287bca73	adding testbenches	2022-02-28 23:55:42 +01:00
Erick	680094e4e8	verilog predefined gates (re)definition	2022-02-28 23:53:53 +01:00
Erick	af47b1fe38	fixed typo	2022-02-22 13:19:11 +01:00
Erick	2fde4d5bf5	created predefined gates in verilog	2022-02-22 13:06:51 +01:00