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bcb06dae6a
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Create mux.v (multiplexer gate)
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2022-02-28 23:56:05 +01:00 |
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90287bca73
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adding testbenches
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2022-02-28 23:55:42 +01:00 |
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680094e4e8
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verilog predefined gates (re)definition
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2022-02-28 23:53:53 +01:00 |
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e6e955a3b1
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Update README.md
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2022-02-28 23:44:46 +01:00 |
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38e5cd0f52
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Update .gitignore
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2022-02-28 23:44:36 +01:00 |
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af47b1fe38
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fixed typo
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2022-02-22 13:19:11 +01:00 |
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2fde4d5bf5
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created predefined gates in verilog
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2022-02-22 13:06:51 +01:00 |
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4cbdd294fb
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add git files
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2022-02-22 13:06:26 +01:00 |
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63323b9bb6
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Initial commit
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2022-02-15 00:07:24 +01:00 |
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