 Erick
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6999a0702b
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minor fix
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2022-04-07 17:15:16 +02:00 |
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Erick
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09676ffb82
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minor fixes
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2022-03-27 19:00:14 +02:00 |
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Erick
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e568e64264
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created 16-bit cpu
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2022-03-27 18:30:31 +02:00 |
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Erick
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c3d48c6241
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minor changes
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2022-03-27 14:37:02 +02:00 |
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Erick
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724cbc0d52
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create program counter
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2022-03-23 15:09:28 +01:00 |
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Erick
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f93143d860
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create ram16384.sv
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2022-03-23 13:03:58 +01:00 |
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Erick
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85fd2df83a
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output size fix
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2022-03-23 12:45:55 +01:00 |
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Erick
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9098b71ccc
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fixed file name
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2022-03-23 12:36:15 +01:00 |
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Erick
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5277d8fd78
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name changes in ram8 chip used in ram16
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2022-03-23 12:33:56 +01:00 |
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Erick
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c166389176
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create ram512.sv
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2022-03-23 12:33:22 +01:00 |
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Erick
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a52dbe03fc
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Create ram16.sv
16-bit ram chipset
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2022-03-22 16:47:56 +01:00 |
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Erick
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c5413708df
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Create ram8.sv
8-bit ram chipset
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2022-03-22 16:47:44 +01:00 |
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Erick
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3196223e02
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create 16-bit register
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2022-03-22 16:47:13 +01:00 |
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Erick
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5613fba905
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minor fix
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2022-03-22 16:46:55 +01:00 |
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Erick
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3223f3a6af
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Create bit_reg.sv
bit_reg.v is a single bit register that uses a data flipflop
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2022-03-08 15:08:04 +01:00 |
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Erick
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8c70d4384f
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minor fixes in flipflop logic
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2022-03-08 15:07:02 +01:00 |
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Erick
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b5d5fb5a05
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created sr, jk and data flipflops
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2022-03-08 13:54:42 +01:00 |
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Erick
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3ade6ba96a
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create sr flipflop logic
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2022-03-07 02:17:10 +01:00 |
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