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23f2cfea4e
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Update README.md
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2022-03-04 01:40:12 +01:00 |
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613178fc34
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creation of an ALU
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2022-03-04 01:39:07 +01:00 |
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Erick
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52c7210d0c
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Create xor_tb.v
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2022-03-04 01:38:43 +01:00 |
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d65b968e96
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update and debug testbench
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2022-03-04 01:38:36 +01:00 |
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Erick
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9c4b6b7ce4
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Update README.md
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2022-03-04 01:38:09 +01:00 |
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Erick
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53170f5c5a
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various fixes
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2022-03-04 01:38:03 +01:00 |
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Erick
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f598d2d71b
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Update .gitattributes
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2022-03-02 00:33:07 +01:00 |
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21d7b03ec2
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Update .gitignore
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2022-03-02 00:32:55 +01:00 |
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fc71658352
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Create README.md
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2022-03-02 00:32:50 +01:00 |
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a211c76b45
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typo
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2022-03-02 00:32:46 +01:00 |
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001b7886d6
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testbench dump
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2022-03-01 23:35:40 +01:00 |
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0646b73f9a
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gates dump
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2022-03-01 23:35:17 +01:00 |
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540aac9fca
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add demux and testbench
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2022-03-01 00:36:52 +01:00 |
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Erick
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bcb06dae6a
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Create mux.v (multiplexer gate)
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2022-02-28 23:56:05 +01:00 |
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Erick
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90287bca73
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adding testbenches
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2022-02-28 23:55:42 +01:00 |
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Erick
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680094e4e8
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verilog predefined gates (re)definition
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2022-02-28 23:53:53 +01:00 |
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e6e955a3b1
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Update README.md
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2022-02-28 23:44:46 +01:00 |
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38e5cd0f52
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Update .gitignore
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2022-02-28 23:44:36 +01:00 |
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af47b1fe38
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fixed typo
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2022-02-22 13:19:11 +01:00 |
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2fde4d5bf5
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created predefined gates in verilog
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2022-02-22 13:06:51 +01:00 |
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4cbdd294fb
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add git files
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2022-02-22 13:06:26 +01:00 |
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Erick
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63323b9bb6
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Initial commit
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2022-02-15 00:07:24 +01:00 |
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